Performing logic functions in an array of identical circuit elements, each located at a unique intersection of an input and output line in a grid of intersecting input and output lines, is well-known. It is also well-known to perform complex logic functions in a compound arrangement of these arrays called a Programmable Logic Array (PLA) chip by using the outputs of one array as the inputs to another array. U.S. Pat. No. 3,936,812 describes such a PLA on which a number of decoders feed inputs to a first array called a product term generator or an AND array which, in turn, supplies outputs to a second array called a sum of product term generator or an OR array. The outputs of the OR array are then used to control the setting and resetting of a string of latches so that both combinatorial and sequential logic functions can be performed by the PLA. The particular logic functions actually performed by the given PLA are controlled by the locations and number of the active logic circuits in the AND and OR arrays of the PLA and also by how inputs are supplied to the decoders either from off the chip or from the latches.
FIG. 1 illustrates a conventional implementation of a PLA in MOSFET technology where the distinct AND 2 and OR 4 arrays are shown. Inputs to the AND array 2 from the input bit partitioning circuit 8 are on the metal level driving devices 10 in the AND array 2 which are made active by growing thin oxide regions between ground diffusions 11 and product term diffusions 12. Signal outputs from the AND array 2 are transmitted through diffused product term array lines 12. As these product terms enter the OR array 4, they are transformed to the metal level 16 through contacts 14 as shown. The OR array 4 devices 18 are active if a thin oxide region is grown between ground diffusions 19 and output diffusions 20. Outputs from the OR array are on diffused lines 20. Prior art PLA circuits such as this require a relatively large chip area to layout and suffer from an inability to independently test the AND and OR array elements without additional input buffers and output latches. FIG. 1, for clarity, is not optimum since an additional vertical product term line can be placed between ground diffusions for additional density.
Conventional PLA's are programmed by employing a customized photolithographic mask to define thin oxide gate regions for selected ones of a plurality of possible FET array devices. This prior art technique results in PLA products which cannot be subsequently modified to correct errors or to implement logic changes. The mask fabrication process is time consuming and therefore impedes what would otherwise be a rapid LSI logic design technique.